Grape is an array accelerator,
designed from scratch.
Grape blends the programmability of an FPGA with the performance of systolic arrays through a CGRA architecture. Each Grape accelerator contains a grid of functional units which can be programmed and connected to one another to implement most dataflow graphs. Grape is programmed using Juno, a medium-level programming language which supports scheduling code across accelerators and CPUs. Grape is under active development with an anticipated fabrication date of December 2024, and this website will be regularly updated with new content.